1. Field of the Invention
This invention relates to decoupling capacitors, and more specifically to on-chip decoupling capacitors.
2. Background Information
As electronic devices operate at higher frequencies the need for low-inductance power delivery increases. At high frequencies, inductive voltage drop and electronic noise are serious problems for electronic device designers. Small inductance current sources help to ameliorate many of the problems of switching electronic devices at high frequencies. The main source of inductance in electronic devices is the wire leads carrying current to the transistors. Capacitors act as local power sources for transistors. Situating the capacitors closer to the transistors shortens the length of the leads and reduces the inductance of the power delivery system, allowing the transistors to be switched at much greater frequencies. These local capacitors also allow the transistors to operate at higher frequencies for the same power consumption or at the same frequency with less power consumption.
For performance reasons such as above, or other reasons, it may be desired to increase the total capacitance on a die. Generally, in order to achieve large capacitance: (1) capacitor surface area must increase; (2) dielectric constant (K) of the dielectric layer must increase; or (3) dielectric film thickness must to decrease. With the increasing speed of electronic devices, and with shrinking die size, the challenge is to increase the total capacitance on a die within a fixed area. Currently decoupling capacitors are put into the package, but these are high inductance configurations and are limited at high frequencies.
Therefore, there is a need for method and apparatus that increases capacitance without increasing the footprint of an on-chip decoupling capacitor.